Services
Semiconductor
RTL Design and Verification
Wafer Space is one of the premier design and verification experts with experience in design and cutting edge verification using the latest methodologies. Wafer Space has a highly experienced team in design and verification and has successfully taped out many IPs, subsystems and chips
- Micro-architecture Planning
- RTL Implementation
- Functional Verification of IPs and SoCs
- Verification languages: Specman "e" SV, C and Vera
- Methodologies: eRM, VMM, OVM, UVM
- Architecture Planning and implementation
- Detailed Architecture Description
- Feature based Coverage Planning
- Tests planning based on coverpoints – stimulus, response and cornercase
- Analog model integration
- CPF/UPF based simulations
- Power domains based assertion checks
- Gate level sims using cpf netlist
- Assertion based verification
- Interconnection assertion checks
- Protocol compliance checks
- TLM Modeling
- System C models for virtual prototyping
- Netlist Simulations with/without sdf
- Power Estimation
- Simulations using min/typical/max timing
- Power Aware based Gate level sims
Physical Design
With a senior physical implementation team and physical architects specialized in diverse domains, Wafer Space is well positioned to own and execute projects in ownership mode. In addition to full chip partitioning & integration, our team has the experience in defining smart flows to drive optimal PPA closure on complex architectures like CPU core hardening, 1866 DDR3, 28Gbps multi-protocol SerDes, MIPI, CSI/DSI, WLAN and BT. The Wafer Space team has experience in all the major industry standard EDA tools.
- Optimal Process/Technology Identification, Layer Stack finalization, Standard Cell Variant selections, Memory selections and tiling based on PPA requirements
- Physical partition, voltage island & clocking strategy definitions based on Architectural demands
- Hierarchical Synthesis of multi-million gate designs (Low Power Aware)
- Physical Synthesis Methodology development, Constraint development, IP Constraint Integration, Cell Flavor Definitions from scratch
- Scan Insertion, Scan Compression, Memory BIST, Redundancy requirement Analysis & Insertion, logic BIST, JTAG and Boundary Scan
- DVFS, AVS, AVSO handling, At-speed Scan, test clocking, analog testing and pin-muxing (Multi-voltage Aware)
- Test vector generation and ATE post-silicon debug
- IO ring build, Bonding/Package route feasibility Analysis and Custom IP integration
- Prototyping, Multi-voltage aware Partitioning, Feed-through/Bus management, Clock Build specifics, Power Network Synthesis & Grid Design, Budgeting and Die Size Validation
- Fullchip and Block level signal integrity aware signal routing and timing closure
- Static and Dynamic power analysis and violation fixes
- Wire Bond and flipchip based design expertise and ESD simulations
- Expertise in fullchip and block level timing closure with MMMC
- Signal Integrity(crosstalk delay, noise glitch) aware timing closure with OCV/AOCV
- Extraction, timing model build and SSTA
- Fullchip integration of custom IPs, IO ring and MACROs
- Expert knowledge of sub 20nm design rules and Physical verification
- Power, Timing and Physical verification sign-off checks and tapeout
DFT and ATE
The Wafer Space DFT team has expertise in DFT implementation and DFT verification with all the major industry EDA tools. The team's expertise is in implementation and verification in the areas of ATPG, BIST and SCAN. The team also has expertise in Test engineering.
DFT Planning & Architecture
DFT Implementation
ATPG , ATPG verification, ATE patterns & Silicon debug
MBIST Verification ,ATE patterns and silicon debug
Boundary SCAN Verification, ATE patterns and silicon debug
ATE Test Program Development & Production Support
ATE Hardware development and packaging
- Strategies for low test power, low test cost and less test pin utilization, Test pin-muxing, Test clock/Test reset pin identification, planning for on-chip clock insertion.
- Strategies for Mixed-Signal DFT, Hard-IP, Analog blocks
- User Defined register implementation for all concern control bits. On-chip Clock insertion for respective clock domain, TAP controller and Boundary scan insertion,Test-Pinmuxing
- MBIST insertion at block/TOP level, Scan insertion/LBIST insertion, IOwrapper insertion for each DFT blocks, compression/decompression insertion
- Expertize in different format of pattern generation i.e. Verilog, ASCII, different ATE format, Cell-aware pattern generation, Power-aware pattern generation,
- Pattern re-targeting ,Zero-delay as well as timing verification across different SDF corners, ATE pattern generation, and Silicon debug of failing patterns
- Expertize in MBIST verification for Block level as well as Full-Chip level, MBIST verification for repairable and nonrepairable memories.
- No-timing simulation & debug, timing simulation & debug across different SDF corners, ATE pattern generation for MBIST controllers, Silicon debug of failing patterns
- Expertise in BSCAN verification with respect to IEEE 1149.1 & IEE1149.6 protocol
- Simulation debug without and with SDF across different PVT corners, ATE patterns generation for different requirements and silicon debug
- Expertize in ATE test program development for Digital domain, Analog domain, Mixed signal, RF domain, Program development for engineering evaluation as well as production support
- ATE program development and debug support on multiple tester platform, Multi Site program development, program conversion from one platform to another platform, PVT characterization
- Expertize in Load boards, Handler Interface Board, DUT Interface Board-TE
- Expertize in Probe Card, Probe Interface board, Device characterization board, burn-In board
- Expertize in different kind of BGA, Leadframe, Hermetic package through our partners
Emulation and Prototyping
Wafer Space has the expertise in Synopsys Zebu/HAPS, Mentor Veloce and Cadence Palladium emulation platforms. Our team has carried out Emulation of complex multi-million ARM based SoCs for leading semiconductor companies and supported the bring-up of software on a pre-silicon Emulation platform. Wafer space also offers end-to-end standalone FPGA design services which includes RTL development, functional verification using native and third party simulators, Design Synthesis using native & third party synthesizers, Place and route of design to target FPGA using native Place and route tools. On target testing, debugging using native/third party integrated logic analyzers and using test equipment like external logic analyzers & oscilloscopes.
- Architectural Design
- Designs with SoC FPGAs
- IP Development for target FPGAs
- IP Development for target FPGAs
- Conceptual Validation and Algorithm implementation
- IP Porting into FPGAs, Design Partitioning
- Building of custom FPGA platforms
- Experience on how to partition, interface analog & RF IPs/ICs with FPGA-mapped digital design
- Development of HW-SW bring-up Environment
- Design Porting into Emulation Platforms
- Verification Env and Test Development for Emulation Platforms
- HW/SW Co verification with OS
- Xilinx, Altera and Microsemi
- Debugging tools, IDEs for H/W –S/W Co-Design
- Prototyping platforms - HAPS
Analog
The Wafer Space analog team is well versed in analog layout and in AMS modeling and verification. Our Layout expertise includes In-depth expertise on RF, Analog and Power management IPs including PLLs, DC-DC Convertors, DLLs, LDOs, etc in all the leading foundries in all the technology nodes. Our AMS expertise includes both modeling and verification.
- Analog, RF, Power Management IC, Memory
- SerDes, LDO, BGR, DC-DC Converters, Phase Interpolator, ADC, DAC, PLL, Power Regulators, SRAM
- Specialists in high speed and power management designs.
- Third Party IP integration, Analog Ips, Full Chip Integration and sign Off
- Mixed Signal – VHDL, Verilog AMS, WREAL, SystemVerilog Nettype
- Analog – Verilog A
- Expertise in Verilog, VHDL ,SV and UVM
- AMS Verification with Models and Digital designs – Digital/Analog Top
- Verification with Analog Models and SPICE
- SerDes, ADCs, DACs
- IC – LDO, Buck/Boost, ChargePump, Fuel Gauges, GPIOs etc
Embedded
Embedded
Wafer Space has been providing hardware and software design, development and testing services for Automotive, Industrial Control and solutions around IOT technology. The technical team at Wafer Space has experience in complete software development life cycle, with involvement right from requirements analysis stage up to final release and acceptance of the software. With experience in various hardware platforms and processor architectures as well as real time OS platforms, Wafer Space can enable embedded system development involving hardware design, software development and hardware/software integration. With our partner-ecosystem, we can enable functional prototyping, pre-compliance testing and volume manufacturing.
- Custom Applications
- GUI design
- Multimedia
- H.264, MPEG4,AAC, MP3, JPEG
- Open Max, Stagefright, Gstreamer
- Connectivity
- BT, Wifi, NFC, Zigbee & GPS
- BSP, Board-bring up
- Kernel & Drivers (USB, Camera, IO, Display)
- Android
- Linux
- Windows
- RTOS
- ARM, PIC, TI, Freescale, custom
Software and Apps
Software and Apps
The Wafer Space Embedded software team is equipped to deliver Embedded application software and safety-critical embedded systems software across segments such as Automotive, Medical Electronics, Internet-Of-Things, Industrial Automation, Man-Machine Interface software, Embedded control software applications for handhelds on Mobile OS such as Android and iOS. The Wafer Space Expertise includes –
- Android Application Development
- iOS Application Development
- C and Assembly Language based applications for 8, 16 and 32-bit microcontroller and DSP based embedded platforms.
- Customized / Optimized software application development with Low memory footprint for Standard and non-standard input/output based devices.
- Web application optimization for low performance systems in Java enterprise solutions
- E-commerce applications, Content Management System (CMS) and web application solutions.
- Technical expertise in Java technologies and frameworks such as J2EE, JSF, Jquery, Spring, JBoss and others.
- Database solutions based on Hibernate, JPA, MySQL.
- Embedded database Derby and Oracle, Wordpress, Drupal are also part of our skills and expertise.
- Python, GTK and QT Based UI applications for Linux platform.
- Embedded C and C++ based applications for embedded devices.
- Media framework customization and Media streaming server / applications.
- Windows MFC/C# based GUI Application for Portable handhelds.
- System profiling to identify bottlenecks
- Power and performance optimizations
- Component tuning for performance optimization
- Code optimization for low foot-print and faster boot-up.
Semiconductor
RTL Design and Verification
Wafer Space is one of the premier design and verification experts with experience in design and cutting edge verification using the latest methodologies. Wafer Space has a highly experienced team in design and verification and has successfully taped out many IPs, subsystems and chips
RTL Design
- Micro-architecture Planning
- RTL Implementation
Ip And Soc Verfication
- Functional Verification of IPs and SoCs
- Verification languages: Specman "e" SV, C and Vera
- Methodologies: eRM, VMM, OVM, UVM
Environment Architecture
- Architecture Planning and implementation
- Detailed Architecture Description
Coverage Driven Test Plans
- Feature based Coverage Planning
- Tests planning based on coverpoints – stimulus, response and cornercase
Low Power Expertise
- Analog model integration
- CPF/UPF based simulations
- Power domains based assertion checks
- Gate level sims using cpf netlist
Static Formal Verification
- Assertion based verification
- Interconnection assertion checks
- Protocol compliance checks
System C Modeling
- TLM Modeling
- System C models for virtual prototyping
Gate level Simulations
- Netlist Simulations with/without sdf
- Power Estimation
- Simulations using min/typical/max timing
- Power Aware based Gate level sims
Physical Design
With a senior physical implementation team and physical architects specialized in diverse domains, Wafer Space is well positioned to own and execute projects in ownership mode. In addition to full chip partitioning & integration, our team has the experience in defining smart flows to drive optimal PPA closure on complex architectures like CPU core hardening, 1866 DDR3, 28Gbps multi-protocol SerDes, MIPI, CSI/DSI, WLAN and BT. The Wafer Space team has experience in all the major industry standard EDA tools.
Physical Architecture
- Optimal Process/Technology Identification, Layer Stack finalization, Standard Cell Variant selections, Memory selections and tiling based on PPA requirements
- Physical partition, voltage island & clocking strategy definitions based on Architectural demands
RTL Synthesis & Pre-Layout STA
- Hierarchical Synthesis of multi-million gate designs (Low Power Aware)
- Physical Synthesis Methodology development, Constraint development, IP Constraint Integration, Cell Flavor Definitions from scratch
Design-for-Test(DFT)
- Scan Insertion, Scan Compression, Memory BIST, Redundancy requirement Analysis & Insertion, logic BIST, JTAG and Boundary Scan
- DVFS, AVS, AVSO handling, At-speed Scan, test clocking, analog testing and pin-muxing (Multi-voltage Aware)
- Test vector generation and ATE post-silicon debug
Design Planning
- IO ring build, Bonding/Package route feasibility Analysis and Custom IP integration
- Prototyping, Multi-voltage aware Partitioning, Feed-through/Bus management, Clock Build specifics, Power Network Synthesis & Grid Design, Budgeting and Die Size Validation
Signal/Power integrity Closure
- Fullchip and Block level signal integrity aware signal routing and timing closure
- Static and Dynamic power analysis and violation fixes
- Wire Bond and flipchip based design expertise and ESD simulations
Timing Convergence
- Expertise in fullchip and block level timing closure with MMMC
- Signal Integrity(crosstalk delay, noise glitch) aware timing closure with OCV/AOCV
- Extraction, timing model build and SSTA
Fullchip Assembly, Sign-Off Checks & Tape-out
- Fullchip integration of custom IPs, IO ring and MACROs
- Expert knowledge of sub 20nm design rules and Physical verification
- Power, Timing and Physical verification sign-off checks and tapeout
DFT and ATE
The Wafer Space DFT team has expertise in DFT implementation and DFT verification with all the major industry EDA tools. The team's expertise is in implementation and verification in the areas of ATPG, BIST and SCAN. The team also has expertise in Test engineering.
DFT Planning & Architecture
- Strategies for low test power, low test cost and less test pin utilization, Test pin-muxing, Test clock/Test reset pin identification, planning for on-chip clock insertion.
- Strategies for Mixed-Signal DFT, Hard-IP, Analog blocks
DFT Implementation
- User Defined register implementation for all concern control bits. On-chip Clock insertion for respective clock domain, TAP controller and Boundary scan insertion,Test-Pinmuxing
- MBIST insertion at block/TOP level, Scan insertion/LBIST insertion, IOwrapper insertion for each DFT blocks, compression/decompression insertion
ATPG , ATPG verification, ATE patterns & Silicon debug
- Expertize in different format of pattern generation i.e. Verilog, ASCII, different ATE format, Cell-aware pattern generation, Power-aware pattern generation,
- Pattern re-targeting ,Zero-delay as well as timing verification across different SDF corners, ATE pattern generation, and Silicon debug of failing patterns
MBIST Verification ,ATE patterns and silicon debug
- Expertize in MBIST verification for Block level as well as Full-Chip level, MBIST verification for repairable and nonrepairable memories.
- No-timing simulation & debug, timing simulation & debug across different SDF corners, ATE pattern generation for MBIST controllers, Silicon debug of failing patterns
Boundary SCAN Verification, ATE patterns and silicon debug
- Expertise in BSCAN verification with respect to IEEE 1149.1 & IEE1149.6 protocol
- Simulation debug without and with SDF across different PVT corners, ATE patterns generation for different requirements and silicon debug
ATE Test Program Development & Production Support
- Expertize in ATE test program development for Digital domain, Analog domain, Mixed signal, RF domain, Program development for engineering evaluation as well as production support
- ATE program development and debug support on multiple tester platform, Multi Site program development, program conversion from one platform to another platform, PVT characterization
ATE Hardware development and packaging
- Expertize in Load boards, Handler Interface Board, DUT Interface Board-TE
- Expertize in Probe Card, Probe Interface board, Device characterization board, burn-In board
- Expertize in different kind of BGA, Leadframe, Hermetic package through our partners
Emulation and Prototyping
Wafer Space has the expertise in Synopsys Zebu/HAPS, Mentor Veloce and Cadence Palladium emulation platforms. Our team has carried out Emulation of complex multi-million ARM based SoCs for leading semiconductor companies and supported the bring-up of software on a pre-silicon Emulation platform. Wafer space also offers end-to-end standalone FPGA design services which includes RTL development, functional verification using native and third party simulators, Design Synthesis using native & third party synthesizers, Place and route of design to target FPGA using native Place and route tools. On target testing, debugging using native/third party integrated logic analyzers and using test equipment like external logic analyzers & oscilloscopes.
FPGA Design
- Architectural Design
- Designs with SoC FPGAs
- IP Development for target FPGAs
- IP Development for target FPGAs
- Conceptual Validation and Algorithm implementation
ASIC PROTOTYPING
- IP Porting into FPGAs, Design Partitioning
- Building of custom FPGA platforms
- Experience on how to partition, interface analog & RF IPs/ICs with FPGA-mapped digital design
- Development of HW-SW bring-up Environment
EMULATION
- Design Porting into Emulation Platforms
- Verification Env and Test Development for Emulation Platforms
- HW/SW Co verification with OS
TOOL EXPERTISE
- Xilinx, Altera and Microsemi
- Debugging tools, IDEs for H/W –S/W Co-Design
- Prototyping platforms - HAPS
Analog
The Wafer Space analog team is well versed in analog layout and in AMS modeling and verification. Our Layout expertise includes In-depth expertise on RF, Analog and Power management IPs including PLLs, DC-DC Convertors, DLLs, LDOs, etc in all the leading foundries in all the technology nodes. Our AMS expertise includes both modeling and verification.
Layout Domains
- Analog, RF, Power Management IC, Memory
Layout Expertise
- SerDes, LDO, BGR, DC-DC Converters, Phase Interpolator, ADC, DAC, PLL, Power Regulators, SRAM
- Specialists in high speed and power management designs.
- Third Party IP integration, Analog Ips, Full Chip Integration and sign Off
AMS Modelling
- Mixed Signal – VHDL, Verilog AMS, WREAL, SystemVerilog Nettype
- Analog – Verilog A
- Expertise in Verilog, VHDL ,SV and UVM
AMS Verification
- AMS Verification with Models and Digital designs – Digital/Analog Top
- Verification with Analog Models and SPICE
AMS Protocols
- SerDes, ADCs, DACs
- IC – LDO, Buck/Boost, ChargePump, Fuel Gauges, GPIOs etc
Embedded
Embedded
Wafer Space has been providing hardware and software design, development and testing services for Automotive, Industrial Control and solutions around IOT technology. The technical team at Wafer Space has experience in complete software development life cycle, with involvement right from requirements analysis stage up to final release and acceptance of the software. With experience in various hardware platforms and processor architectures as well as real time OS platforms, Wafer Space can enable embedded system development involving hardware design, software development and hardware/software integration. With our partner-ecosystem, we can enable functional prototyping, pre-compliance testing and volume manufacturing.
Applications
- Custom Applications
- GUI design
Middleware
- Multimedia
- H.264, MPEG4,AAC, MP3, JPEG
- Open Max, Stagefright, Gstreamer
- Connectivity
- BT, Wifi, NFC, Zigbee & GPS
System Software
- BSP, Board-bring up
- Kernel & Drivers (USB, Camera, IO, Display)
Operating Systems
- Android
- Linux
- Windows
- RTOS
Platforms
- ARM, PIC, TI, Freescale, custom
Software and Apps
Software and Apps
The Wafer Space Embedded software team is equipped to deliver Embedded application software and safety-critical embedded systems software across segments such as Automotive, Medical Electronics, Internet-Of-Things, Industrial Automation, Man-Machine Interface software, Embedded control software applications for handhelds on Mobile OS such as Android and iOS. The Wafer Space Expertise includes –
Application Development for Mobile OS
- Android Application Development
- iOS Application Development
Custom Application Development
- C and Assembly Language based applications for 8, 16 and 32-bit microcontroller and DSP based embedded platforms.
- Customized / Optimized software application development with Low memory footprint for Standard and non-standard input/output based devices.
Enterprise software applications - Web / Cloud applications
- Web application optimization for low performance systems in Java enterprise solutions
- E-commerce applications, Content Management System (CMS) and web application solutions.
- Technical expertise in Java technologies and frameworks such as J2EE, JSF, Jquery, Spring, JBoss and others.
- Database solutions based on Hibernate, JPA, MySQL.
- Embedded database Derby and Oracle, Wordpress, Drupal are also part of our skills and expertise.
Linux and Windows OS Application Development
- Python, GTK and QT Based UI applications for Linux platform.
- Embedded C and C++ based applications for embedded devices.
- Media framework customization and Media streaming server / applications.
- Windows MFC/C# based GUI Application for Portable handhelds.
Embedded Software Performance Optimization and Migration
- System profiling to identify bottlenecks
- Power and performance optimizations
- Component tuning for performance optimization
- Code optimization for low foot-print and faster boot-up.